I am currently working at the SPE Laboratory (Sciences Physiques pour l’Environnement) Laboratory of the University of Corsica, UMR CNRS 6134. My main interests concern the modeling and simulation of complex systems (like digital systems) using distributed or sequential discrete event approaches.
The domain of concurrent fault simulation for digital circuits described at the RT-level is currently under heavy researches. The goal of these researches is to define a fast and efficient methodology for the validation of test patterns very early in the design flow. We propose a new approach for the modeling and the concurrent simulation of behavioral faults for digital circuits described in the VHDL language, using a discrete event approach. This methodology, based on the DEVS formalism, is implemented in a working prototype using the pythonDEVS tool, and experimental results show the correctness of our approach and the efficiency of our behavioral fault concurrent simulator called BFS-DEVS. The fault model used to validate our results is essentially based on the stuck-at fault model since a good simple stuck-at faults coverage rate implies a good real faults coverage rate.